1. Field of the Invention
The present invention relates generally to a method and apparatus for locating short circuit faults in an integrated circuit layout, and more particularly to locating faults due to incorrectly connected nets in IC layouts such as in extracted or reverse engineered integrated circuit layouts.
2. Related Art
During fabrication of an integrated circuit (IC), a layout corresponding to the physical characteristics of the IC is designed and used as a mask set. This mask set is then overlaid on a wafer of silicon. The IC layout comprises a series of nets representing the arrangement of the various conductive layers. A net is defined as a continuous path of electrically conductive wiring within an electrical wire network, this is normally represented in layout as sets of electrically connected polygons.
A similar layout is created during reverse engineering of an IC. This layout also comprises a series of polygons representing the arrangement of the various conductive layers. Unlike the previous case, however, this layout is used to extract the electrical conductive circuitry that make up the IC.
Incorrect placement of polygons or contact materials connecting adjacent conductive layers (vias), results in the connection of one net to another on the layout. Dirt or debris on a de-layered IC can cause incorrect layout extraction if the software processes the dirt or debris as conductive wiring connecting two or more existing nets. Further a software layout tool placing nets on an IC may erroneously connect two nets together. This results in a malfunctioning IC or an incorrect circuit extraction.
If only geometric information is available to the programs analyzing the layout information, then it is typically not possible to precisely locate the position of the incorrectly placed polygon(s).
U.S. Pat. No. 5,949,986, which issued to Riley et al on Sep. 7, 1999, teaches a way to extract signal connectivity information from the layout. It allows, during the verification phase, the ability to locate circuits that are shorted because of error. It does not, however, provide an efficient way to locate actual point(s) where the error is made. If major signals are shorted, for example POWER and GROUND buses, the manual inspection to find the error is very time consuming since these busses account for up to half of the total wiring capacity.
Other solutions involve a binary search of the layout. The layout is cut in half, and each half is investigated for the presence of shorts between signals. The process continues until the short is located. However, this algorithm involves serious manual interaction, and is applicable only for locating a short that occurs in a single point.
Therefore there is a need for a new solution that can precisely locate short circuits in an IC layout without spending a lot of processing time.